1. Field of the Invention
The present invention relates to a forward/inverse discrete cosine transform (referred to hereinafter as DCT) circuit using a distributed arithmetic processing manner.
2. Description of the Prior Art
Generally, conventional 8.times.1 DCT associated techniques relate to a forward/inverse DCT circuit using a distributed arithmetic processing manner. One example of such a conventional 8.times.1 DCT associated technique is disclosed in U.S. Pat. No. 5,357,453. The '453 patent shows a method for efficiently implementing a DCT circuit which is capable of converting a video signal into a frequency signal in real time.
FIG. 1 shows a conventional one-dimensional DCT circuit which performs forward and inverse 8.times.1 DCT operations using the distributed arithmetic processing manner. The operation and construction of the conventional 8.times.1 DCT circuit are disclosed in detail in the '453 patent.
The 8.times.1 DCT implementation in FIG. 1 can be extended to an 8.times.8 DCT. An example of such an 8.times.8 DCT implementation is shown in block form in FIG. 2. The representative method of 8.times.8 DCT implementation is to sequentially perform the 8.times.1 DCT operation with respect to an input 8.times.8 block in the order of row, a row/column substitution operation and the 8.times.1 DCT operation with respect to the input 8.times.8 block in the order of column. Of course, a circuitry is provided to perform the row/column substitution operation between the 8.times.1 DCT operation in the order of row and the 8.times.1 DCT operation in the order of column. As a result, the 8.times.8 DCT implementation is provided with two 8.times.1 DCT circuits, each of which is shown in FIG. 1, and a row/column substitution circuit, as shown in FIG. 2.
The 8.times.8 inverse DCT (referred to hereinafter as IDCT) operation is performed in the reverse order of the 8.times.8 forward DCT operation. Namely, the 8.times.8 IDCT operation is performed by sequentially carrying out the 8.times.1 IDCT operation with respect to DCT coefficients in the order of column, the row/column substitution operation and the 8.times.1 IDCT operation with respect to the DCT coefficients in the order of row. As a result, original pixels are restored.
The 8.times.8 DCT implementation requires no additional circuitry in performing the forward and inverse 8.times.8 DCT operations, because the conventional 8.times.1 DCT circuits of the same construction support both the forward and inverse 8.times.8 DCT operations.
As mentioned above, the two-dimensional 8.times.8 DCT operation is performed by using the conventional 8.times.1 DCT circuit. The compression efficiency of an image compression coding process is determined according to the size of a block to be DCT-processed. Namely, in the case where the block is small in size, it is readily processed but reduced in the compression efficiency. On the contrary, in the case where the block is large in size, it is increased in the compression efficiency but difficult to process. In other words, a larger image size is desirable in view of the compression efficiency, but has a difficulty in processing.
The sizes of blocks to be DCT-processed are 2.times.2, 4.times.4, 8.times.8, 16.times.16 and 32.times.32. The 4.times.4 and 8.times.8 block sizes among the above-listed block sizes are widely used in the standard compression/expansion coding process. In particular, the JPEG, H.261 AND MPEG standards prescribe the process of only 8.times.8 block.
However, in the digital video cassette recorder (referred to hereinafter as DVCR) standards, the size of an input block to be DCT-processed is determined according to a block motion. Namely, in the case where little block motion is present, an 8.times.8 DCT is processed. However, in the case where a large block motion is present, two 4.times.8 DCTs are processed by performing addition and subtraction operations with respect to two vertically adjacent pixels in block. Such a DCT process of different block sizes is performed for enhancing the coding efficiency and picture quality. However, the conventional 8.times.8 DCT processing circuit requires a large number of additional components to process two 4.times.8 DCTs.